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HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 16 MBit Synchronous DRAM
Advanced Information
*
High Performance:
-8 fCK(max.) tCK3 tAC3 tCK2 tAC2 125 8 6 10 6 -10 100 10 7 13.3 8 Units MHz ns ns ns ns
* * * * * * * * * * *
Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge
Data Mask for Read / Write control (x4, x8) Dual Data Mask for byte control ( x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles / 64 ms Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface Plastic Packages: P-TSOPI-44 400mil width ( x4, x8 ) P-TSOPII -50 400 mil width ( x 16 ) -8 version for PC100 applications
* * * * * * *
Fully Synchronous to Positive Clock Edge 0 to 70 C operating temperature Dual Banks controlled by A11 ( Bank Select) Programmable CAS Latency : 2, 3 Programmable Wrap Sequence : Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 full page(optional) for sequencial wrap around
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The HYB39S16400/800/160BT are dual bank Synchronous DRAM' based on the die revisions " " s D, & " and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16 E" respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS'advanced 16MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages. These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
4.98
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Ordering Information
Type Ordering Code Package Description
LVTTL-version:
HYB 39S16400BT-8 HYB 39S16400BT-10 HYB 39S16800BT-8 HYB 39S16800BT-10 HYB 39S16160BT-8 HYB 39S16160BT-10 P-TSOPII-44 (400mil) P-TSOPII-44-(400mil) P-TSOPII-44-(400mil) P-TSOPII-44 (400mil) P-TSOPII-50 (400mil) P-TSOPII-50-(400mil) 125MHz 2B x 2M x 4 SDRAM 100MHz 2B x 2M x 4 SDRAM 125MHz 2B x 1M x 8 SDRAM 100MHz 2B x 1M x 8 SDRAM 125MHz 2B x 512k x 16 SDRAM 100MHz 2B x 512k x 16 SDRAM
Pin Description and Pinouts:
CLK CKE CS RAS CAS WE A0-A10 A11 (BS) Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ DQM, LDQM, UDQM Vdd Vss Vddq Vssq NC Data Input /Output Data Mask Power (+3.3V) Ground Power for DQ' (+ 3.3V) s Ground for DQ' s not connected
Semiconductor Group
2
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Vdd NC Vssq DQ0 Vddq NC Vssq DQ1 Vddq NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Vss NC Vssq DQ3 Vddq NC Vssq DQ2 Vddq NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss
Vdd DQ0 Vssq DQ1 Vddq DQ2 Vssq DQ3 Vddq NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Vss DQ7 Vssq DQ6 Vddq DQ5 Vssq DQ4 Vddq NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss
HYB39S16400BT 2 Bank x 2MBit x 4 TSOPII-44 ( 400 mil x 725 mil) Vdd DQ0 DQ1 Vssq DQ2 DQ3 Vddq DQ4 DQ5 Vssq DQ6 DQ7 Vddq LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 Vssq DQ13 DQ12 Vddq DQ11 DQ10 Vssq DQ9 DQ8 Vddq NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss
HYB39S16800BT 2 Bank x 1MBit x 8 TSOPII-44 ( 400 mil x 725 mil )
HYB39S16160BT 2 Bank x 512kbit x 16 TSOPII-50 ( 400 mil x 825 mil )
Semiconductor Group
3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
Type
Input
Signal Polarity
Pulse
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the rising Edge edge of the clock. Active High Active Low Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby inititiates either the Power Down mode, Suspend mode or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organisation. 4M x 4 SDRAM CAn = CA9 2M x 8 SDRAM CAn = CA8 1M x 16 SDRAM CAn = CA7 In addition to the column address, A10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low=bank A, high=bank B). If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with A11 to control which bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regardless of the state of A11. If A10 is low, then A11 is used to define which bank to precharge.
CKE
Input
Level
CS RAS, CAS WE
Input
Pulse
Input
Pulse
A0 A10
Input
Level
--
A11 (BS) DQx
Input Input Output
Level Level
-- --
Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B. Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic.
DQM LDQM UDQM
Input
Pulse
Active High
VDD, VSS VDDQ VSSQ
Supply Supply -- --
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Semiconductor Group
4
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Row Decoder
2048
2048 x 1024 Memory Bank A
CKE
CKE Buffer Self Refresh Clock
1024
Row Address Counter Bank A Row/Column Select Predecode A 3 Sequential Control Bank A
Sense Amplifiers Column Decoder and DQ Gate 4 11 8 Data Latches Data Input/Output Buffers
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS)
CLK Buffer
Address Buffers (12)
12
8 12 11 Mode Register 8 Sequential Control Bank B
DQ0 DQ1 DQ2 DQ3
CS
CS Buffer 11 RAS Buffer Command Decoder Predecode B Bank B Row/Column Select
3
Data Latches 8
RAS
Column Decoder and DQ Gate Sense Amplifiers 1024 2048 Row Decoder 2048 Memory Bank B 2048 x 1024
CAS
CAS Buffer
WE DQM
WE Buffer
DQM Buffer
Block Diagram for HYB39S16400BT (2 banks x 4M x 4 SDRAM)
Semiconductor Group
5
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Row Decoder Row Decoder
2048
2048 x 512 Memory Bank A
CKE
CKE Buffer Self Refresh Clock
1024
512
Row Address Counter Bank A Row/Column Select
8 Sense Amplifiers Sense Amplifiers Column Decoder and DQ Gate Column Decoder and DQ Gate 8 8 11 Predecode A 8 Data Input/Output Buffers 8
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS)
CLK Buffer
Address Buffers (12)
12
3
Sequential Control Bank A
Data Latches Data Latches 8 8
12
11
Mode Register 8 Sequential Control Bank B
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
CS Buffer 11 Predecode B RAS Buffer Command Decoder
3
8
Data Latches 8
RAS
Bank B Row/Column Select
8
Column Decoder and DQ Gate Sense Amplifiers 512 2048 Memory Bank B Memory Bank B 2048 x 512 2048 x 1024
CAS
CAS Buffer
8
DQM
DQM Buffer
Block Diagram for HYB39S16800BT (2 banks x 1M x 8 SDRAM)
Semiconductor Group
6
Row Decoder Row Decoder
WE
WE Buffer
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Row Decoder Row Decoder Row Decoder Row Decoder
2048 x 512 Memory Bank A 2048 x 256 Memory Bank A 2048 1024 16 512 1024 256
CKE
CKE Buffer Self Refresh Clock
Row Address Counter Bank A Row/Column Select
16
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS)
CLK Buffer
16 11 Predecode A 3 Sequential Control Bank A
8
8 8 Data Latches Data Latches Data Latches Data Latches 16 8
8
Address Buffers (12)
12
12
11 Mode Register 8 Sequential Control Bank B
CS
CS Buffer 11 Predecode B RAS Buffer Command Decoder
3
16
Data Latches Data Latches 8
RAS
Bank B Row/Column Select
16
Column Decoder and DQ Gate Column Decoder and DQ Gate Sense Amplifiers 256
CAS
CAS Buffer
16
Sense Amplifiers
Row Decoder Row Decoder Row Decoder Row Decoder
WE
WE Buffer
2048 Memory Bank B Memory Bank B 2048 x B Memory Bank256 2048 x 1024 Memory Bank B 2048 x 512 2048 x 1024
UDQM
DQM Buffer
LDQM
DQM Buffer
Block Diagram for HYB39S16160BT (2 banks x 512k x 16 SDRAM)
Semiconductor Group
7
Data Input/Output Buffers
Sense Amplifiers Sense Amplifiers Sense Amplifiers Column Decoder and DQ Gate Sense Amplifiers Column Decoder and DQ Gate Column Decoder and DQ Gate Column Decoder and DQ Gate
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the most important operation commands.
Operation Standby, Ignore RAS, CAS, WE and Address Row Address Strobe and Activating a Bank Column Address Strobe and Read Command Column Address Strobe and Write Command Precharge Command Burst Stop Command Self Refresh Entry Mode Register Set Command Write Enable/Output Enable Write Inhibit/Output Disable No Operation (NOP)
CS H L L L L L L L X X L
RAS X L H H L H L L X X H
CAS X H L L H H L L X X H
WE X H H L L L H L X X H
(L/U)DQM X X X X X X X X L H X
Mode Register For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed in the SDRAM mode register. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by reexecuting the mode set command. Both banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the following table.
Semiconductor Group
8
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
BS A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register (Mx)
Operation Mode
M11 M10 M9 M8 M7 0 X 0 X 0 1 0 0 0 0 Mode Normal Multiple Burst with Single Write
Burst Type
M3 0 1 Type Sequential Interleave
Burst Length CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Latency Reserve 1 2 3 Reserve Reserve Reserve Reserve M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Length Sequential 1 2 4 8 Reserve Reserve Reserve Full Page*) Interleave 1 2 4 8 Reserve Reserve Reserve Reserve *) optional
Sequential Burst Addressing 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6
Interleave Burst Addressing 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Semiconductor Group
9
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Read and Write Access Mode When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is 2' then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 . `, Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM' burst read or write accesses on any column s, address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two banks can realize fast serial data access modes among many different pages. Once two banks are activated, column to column interleave operation can be done between two different pages. Refresh Mode SDRAM has two refresh modes, a CAS before RAS (CBR) automatic refresh and a self refresh. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command.
Semiconductor Group
10
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
DQM Function DQM has two functions for data I/O read write operations. During reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency t DQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t DQW = zero clocks). Suspend Mode During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency t CSL ). Power Down In order to reduce standby power consumption, a power down mode is available. Bringing CKE low enters the power down mode and all of receiver circuits are gated. All banks must be precharged before entering this mode. One clock delay is required for mode entry and exit. The Power Down mode does not perform any refresh operation. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock after the Read Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay form the last data-in for CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as tDPL . Precharge Command If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the following list. The precharge command may be applied coincident with the last of burst reads for CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require a time tDPL from the last burst data to apply the precharge command.
Bank Selection by Address Bits A10 Bank A Only Bank B Only Both A and B Low Low High A11 Low High Don' Care t
Semiconductor Group
11
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Power Up Procedure All Vdd and Vddq must reach the specified voltage no later than any of input signal voltages. An initial pause of 200 sec is required after power on. All banks have to be precharged and a minimum of 2 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
12
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 150 C Input/output voltage .............................................................................. - 0.5 to min(Vcc+0.5, 4.6) V Power supply voltage VDD / VDDQ.......................................................................... - 1.0 to + 4.6 V Power Dissipation............................................. ................................................................ ..........1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operation and Characteristics for LV-TTL versions: TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < Vddq, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Notes:
1. All voltages are referenced to VSS. 2. Vih may overshoot to Vcc + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 10 10 2.0 - 0.3 2.4 - - 10 - 10
Unit Notes V V V V A A 1, 2, 3 1, 2, 3 3 3
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (CLK) Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Symbol
Values min. max. 4.0 5.0 6.5 2.5 2.5 4.0
Unit pF pF pF
CI1 CI2 CIO
Input / Output capacitance (DQ)
Semiconductor Group
13
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, VCC = 3.3V 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter Operating Current
Symbol
Test Condition
Burst Length = 4 trc>=trc (min.) tck>=tck(min.), Io = 0mA 2 bank interleave operation CKE<=VIL(max), tck>=tck(min.) tCK=infinite
CAS
Latency
-8 80 115 125 3 2 20
-10 65 90 100 3 2 20 mA mA mA mA mA
Note
max. max.
1, 2
Icc1
1 2 3
Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power down Mode Active Standby Current in Power Down Mode
Icc2P
Icc2PS CKE<=VIL(max), Icc2N
CKE>=VIH(min), tck>=tck(min.) input signals changed once in 3 cycles tCK=infinite, input signals are stable
mA CS=
High
Icc2NS CKE>=VIH(min),
10
10
mA
Icc3P
CKE<=VIL(max), tck>=tck(min.) tCK=infinite, inpit signals are stable
3 2
3 2
mA mA
Icc3PS CKE<=VIL(max),
Active Standby Current in Nonpower Down Mode Burst Operating Current Auto (CBR) Refresh Current Self Refresh Notes:
Icc3N
CKE>=VIH(min), tck>=tck(min.), changed once in 3 cycles tCK=infinite, input signals are stable
25
25
mA CS=
High, 1
Icc3NS CKE>=VIH(min),
15
15
mA
Icc4
Burst Length = full page trc = infinite tck >= tck (min.), IO = 0 mA 2 banks activated trc>=trc(min)
1 2 3 1 2 3
50 80 120 75 95 115
1 1
40 65 95 60 75 90 1
mA
1, 2
Icc5
mA mA mA mA
1, 2
Icc6
CKE=<0,2V
1, 2
1. The specified values are valid when addresses are changed no more than three times during trc(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). 2. The specified values are valid when data inputs (DQ' are stable during tRC(min.). s)
Semiconductor Group
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HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
AC Characteristics 1)2)3) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -8
min max min
Unit
-10
max
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time - - - - 3 3 0.5 125 100 6 6 - - 10 - - - - 3 3 0.5 100 75 7 8 - - 10 MHz MHz 2, 4 ns ns ns ns ns 8 10 - - 10 12 - - s ns ns
tCH tCL tT
Setup and Hold Times
Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up time Power Down Mode Entry Time
tIS tIH tCKS tCKH tRSC tSB
2 1 2 1 16 0
- - - - - 8
3 1 3 1 20 0
- - - - - 10
ns ns ns ns ns ns
5 5 5 5
Common Parameters
Row to Column Delay Time Row Active Time Row to Column Delay Time Row Precharge Time Row Cycle Time Activate(a) to Activate(b) Command period
tRCD tRAS tRCD tRP tRC tRRD
20 45 20 20 70 16
-
100k
24 60 24 24 90 20
-
100k
ns ns ns ns ns ns
6 6 6 6 6 6
- - - -
- - - -
Semiconductor Group
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HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Parameter
Symbol
Limit Values -8
min max min
Unit
-10
max
CAS(a) to CAS(b) Command period
tCCD
1
-
1
-
CLK
Refresh Cycle
Refresh Period (4096 cycles) Self Refresh Exit Time
tREF tSREX
- 10
64
- 10
64
ms ns
Read Cycle
Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tOH tLZ tHZ tDQZ
3 0 3 2
- - 8 -
3 0 3 2
- - 10 -
ns ns ns CLK
2
8
Write Cycle
Write Recovery Time DQM Write Mask Latency Write Latency
tWR tDQW tWL
8 0 0
- - -
10 0 0
- - -
ns CLK CLK
Frequency vs. AC Parameter Relationship Table: -8 -parts
CL 125 MHz 100 MHz 3 2 tRC 9 7 tRAS 6 5 tRP 3 2 tRRD 2 2 tRCD 3 2 tCCD 1 1
tWL
0 0
tWR 1 1
-10 -parts:
CL 100 MHz 75 MHz 3 2 tRC 8 7 tRAS 6 5 tRP 3 2 tRRD 2 2 tRCD 3 2 tCCD 1 1 WL 0 0 tWR 1 1
Semiconductor Group
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HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD
+ 1.4 V 50 Ohm Z=50 Ohm I/O
tT
INPUT
1.4V
50 pF
tAC tLZ tOH
tAC
I/O 50 pF
OUTPUT
1.4V
Measurement conditions for tac and toh
tHZ
fig.1
3. If clock rising time is longer than 1 ns, a time (t T/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (t T -1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
Semiconductor Group
17
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Package Outlines: Plastic Package P-TSOPII-44 ( 400mil, 0.8mm lead pitch)
Thin small outline package, SMD
GLX05862
TSOP-44 (400).WMF
Plastic Package P-TSOPII-50 ( 400mil, 0.8mm lead pitch) Thin small outline package, SMD
0.1 +0.05 1+0.05 -
1.2 max
10.16 +0.13 -
0.8 0.4 +0.05 -0.1 0.2
M
0.5+0.1 50x 0.1 11.76 +0.2 -
50
26
1 20.95 +0.13 1)
Index marking
25
-
1) Does not include plastic or metal protusion of 0.25 max. per side
Semiconductor Group
18
0.15 +0.06 -0.0
3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM Timing Diagrams
1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Read & Write with Auto-Precharge 7.1 Burst Write with Auto Precharge 7.2 Burst Read with Auto Precharge 8. Burst Termination 8.1 Termination of a Burst Read Operation 8.2 Termination of a Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Clock Suspension (using CKE) 12.1 Clock Suspension During Burst ReadCAS Latency = 1 12. 2 Clock Suspension During Burst ReadCAS Latency = 2 12. 3 Clock Suspension During Burst ReadCAS Latency = 3 12. 4 Clock Suspension During Burst Write CAS Latency = 1 12. 5 Clock Suspension During Burst Write CAS Latency = 2 12. 6 Clock Suspension During Burst Write CAS Latency = 3 13. Power Down Mode and Clock Suspend 14. Auto Refresh (CBR) 15. Self Refresh ( Entry and Exit) 16. Random Column Read ( Page within same Bank) 16.1 CAS Latency = 1 16.2 CAS Latency = 2 16.3 CAS Latency = 3 17. Random Column Write ( Page within same Bank) 17.1 CAS Latency = 1 17.2 CAS Latency = 2 17.3 CAS Latency = 3
Semiconductor Group
19
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM Timing Diagrams (cont' d)
18. Random Row Read ( Interleaving Banks) 18.1 CAS Latency = 1 18.2 CAS Latency = 2 18.3 CAS Latency = 3 19. Random Row Write ( Interleaving Banks) 19.1 CAS Latency = 1 19.2 CAS Latency = 2 19.3 CAS Latency = 3 20. Full Page Read Cycle (optional feature) 20.1 CAS Latency = 1 20.2 CAS Latency = 2 20.3 CAS Latency = 3 21. Full Page Write Cycle (optional feature) 21.1 CAS Latency = 1 21.2 CAS Latency = 2 21.3 CAS Latency = 3 22. Precharge Termination of a Burst 22.1 CAS Latency = 1 22.2 CAS Latency = 2 22.3 CAS Latency = 3
Semiconductor Group
20
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 1. Bank Activate Command Cycle
(CAS latency = 3)
T0 CLK
..........
T1
T
T
T
T
T
ADDRESS
Bank A Row Addr.
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
tRCD
tRRD
NOP Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate
COMMAND
: " or " H" L"
Bank A Activate
NOP
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 1, 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
tCK1, DQ' s
CAS latency = 2
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
tCK2, DQ' s
CAS latency = 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
tCK3, DQ' s
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
Semiconductor Group
21
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
tCK1, DQ' s
CAS latency = 2
DOUT A 0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
tCK2, DQ' s
CAS latency = 3
DOUT A 0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
tCK3, DQ' s
DOUT A0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
DQM
tDQZ
tDQW
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ' s
: " " or " H L"
DOUT A 0 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
Semiconductor Group
22
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 1, 2)
T0 CLK
tDQW
T1
T2
T3
T4
T5
T6
T7
T8
DQM
tDQZ
1 Clk Interval BANK A ACTIVATE
COMMAND
NOP
NOP
NOP
READ A
WRITE A
NOP
NOP
NOP
CAS latency = 1
tCK1, DQ' s
Must be Hi-Z before the Write Command CAS latency = 2
DIN A0
DIN A1
DIN A2
DIN A3
tCK2, DQ' s
: " " or " H L"
DIN A0
DIN A1
DIN A2
DIN A3
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 3
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
CAS latency = 1
tCK1, DQ' s
CAS latency = 2
DOUT A 0
DOUT A1
DOUT A 2 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
DOUT A 0
DOUT A 1
DIN B0
DIN B1
DIN B2
tCK2, DQ' s
CAS latency = 3 DOUT A 0 DIN B0 DIN B1 DIN B2
tCK3, DQ' s
: " or " H" L"
Semiconductor Group
23
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 5. Burst Write Operation
(Burst Length = 4, CAS latency = 1, 2, or 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ' s
DIN A0
DIN A1
DIN A2
DIN A3
don' care t
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 1, 2, or 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval
DQ' s
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
Semiconductor Group
24
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
tCK1, DQ' s
CAS latency = 2
DIN A0
DOUT B 0
DOUT B 1
DOUT B2
DOUT B 3
tCK2, DQ' s
CAS latency = 3
DIN A0
don' care t
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
tCK3, DQ' s
DIN A0
don' care t
don' care t
DOUT B0
DOUT B 1
DOUT B 2
DOUT B 3
Input data for the Write is ignored.
Input data must be removed from the DQ' at least one clock s cycle before the Read dataAPpears on the outputs to avoid data contention.
7.1 Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 1, 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
BANK A ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
tDPL
CAS latency = 1 DIN A0 DIN A1
tRP
DQ' s
CAS latency = 2
tDPL
* *
tDPL
tRP
DQ' s
CAS latency = 3
DIN A0
DIN A1
tRP
DQ' s
DIN A0
DIN A1
Bank can be reactivated after trp
*
Begin Autoprecharge
*
Semiconductor Group
25
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 1, 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A with AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
* *
tRP
DOUT A 1 DOUT A 2 DOUT A 3
tCK1, DQ' s
CAS latency = 2
DOUT A 0
tRP
DOUT A 0 DOUT A 1 DOUT A 2 DOUT A 3
tCK2, DQ' s
CAS latency = 3
tCK3, DQ' s
*
tRP
DOUT A 0 DOUT A 1 DOUT A 2 DOUT A 3
Bank can be reactivated after trp
*
Begin Autoprecharge
8.1 Termination of a Burst Read Operation
(CAS latency = 1, 2, 3 / Burst Length = 8)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
CAS latency = 1
tCK1, DQ' s
CAS latency = 2
DOUT A0
The burst ends after a delay equal to the CAS latency. DOUT A 1 DOUT A 2 DOUT A 3
tCK2, DQ' s
CAS latency = 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
tCK3, DQ' s
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
Semiconductor Group
26
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM 8.2 Termination of a Burst Write Operation
(CAS Laency = 1, 2, 3, Burst Length = 8)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
CAS latency = 1,2,3
DQ' s
DIN A0
DIN A1
DIN A2
don' care t
Input data for the Write is masked.
Semiconductor Group
27
\
9.1 AC Parameters for Write Timing
Burst Length = 4, CAS Latency = 2
T6 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T7 T8 T9 T2 T3 T4 T5
T0
T1
CLK tCK2 tCS tCH
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
Semiconductor Group
tCH tCKH
tCL
CKE
tCKS
CS
RAS
CAS
28
WE
BA tAH
RBx RAy RAz RBy
AP
RAx
tAS
CAx RBx CBx RAy RAy RAz RBy
Addr
RAx
DQM tRCD tRC
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0
tDS tDH
Ay1 Ay2
tDPL
Ay3
tRP
tRRD
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
\
9.2 AC Parameters for Read Timing
Burst Length = 2, CAS Latency = 2
T3 T10 T11 T12 T13 T4 T5 T6 T7 T8 T9 T0 T1 T2
CLK tCK2 tCS tCKS tCH
Begin Auto Precharge Bank B
Semiconductor Group
tCH tCL tCKH
CKE
CS
RAS
CAS
29
WE
BA tAH
RAx RBx RAy
AP tAS
RAx CAx RBx
Addr tRRD
RBx
RAy
tRAS tRC tAC2 tRCD tLZ tAC2 tOH
Ax0
DQM
tHZ
Ax1 Bx0
tRP tHZ
Bx1
DQ
Activate Command Bank A
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
\
10. Mode Register Set
T2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T3 T4 T5 T6 T7 T8 T9
T0
T1
Semiconductor Group
CLK
CKE 2 Clock min.
CS
RAS
CAS
30
Address Key Mode Register Set Command Any Command
WE
BA
AP
Addr
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Precharge Command All Banks
\
11. Power on Sequence and Auto Refresh (CBR)
T T1 T T T T T T T T T T T T T T T T T T T
T0
T
Semiconductor Group
CLK
CKE Minimum of 2 Refresh Cycles are required 2 Clock min.
High level is required
CS
RAS
CAS
31
Address Key
WE
BA
AP
Addr
DQM tRP tRC
DQ
Hi-Z
Precharge 1st Auto Refresh Command Command All Banks
2nd Auto Refresh Command
Mode Register Set Command
Any Command
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Inputs must be stable for 200s
\
12.1 Clock Suspension During Burst Read (Using CKE) (1 of 3)
Burst Length = 4, CAS Latency = 1
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK1
CKE
CS
RAS
CAS
32
WE
BA
AP
RAx
Addr
RAx
DQM tHZ
Ax0 Ax1 Ax2 Ax3
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
12.2 Clock Suspension During Burst Read (Using CKE) (2 of 3)
Burst Length = 4, CAS Latency = 2
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK2
CKE
CS
RAS
CAS
33
WE
BA
AP
RAx
Addr
RAx
DQM tHZ
Ax0 Ax1 Ax2 Ax3
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
12.3 Clock Suspension During Burst Read (Using CKE) (3 of 3)
Burst Length = 4, CAS Latency = 3
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK3
CKE
CS
RAS
CAS
34
Ax0 Ax1 Ax2 Ax3 Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles
WE
BA
AP
RAx
Addr
RAx
DQM tHZ
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Clock Suspend 3 Cycles
\
12.4 Clock Suspension During Burst Write (Using CKE) (1 of 3)
Burst Length = 4, CAS Latency = 1
T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T12 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK1
CKE
CS
RAS
CAS
35
DAx0 DAx1 DAx2 DAx3
WE
BA
AP
RAx
Addr
RAx
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
12.5 Clock Suspension During Burst Write (Using CKE) (2 of 3)
Burst Length = 4, CAS Latency = 2
T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T12 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK2
CKE
CS
RAS
CAS
36
DAx0 DAx1 DAx2 DAx3 Clock Suspend 1 Cycle Write Command Bank A Clock Suspend 2 Cycles Clock Suspend 3 Cycles
WE
BA
AP
RAx
Addr
RAx
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
\
12.6 Clock Suspension During Burst Write (Using CKE) (3 of 3)
Burst Length = 4, CAS Latency = 3
T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T12 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
CAx
tCK3
CKE
CS
RAS
CAS
37
DAx0 DAx1 DAx2 DAx3 Clock Suspend 1 Cycle Write Command Bank A
WE
BA
AP
RAx
Addr
RAx
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
\
13. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2
T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 T2 T3 T4 T5 T6
T0
T1
CLK tCKSP tCKSP
Semiconductor Group
CAx
tCK2
CKE
CS
RAS
CAS
38
WE
BA
AP
RAx
Addr
RAx
DQM tHZ
Ax0 Ax1 Ax2 Ax3
DQ
Hi-Z
Activate Command Bank A Clock Suspend Mode Exit
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Power Down Mode Entry
Power Down Mode Exit Any Command
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Clock Suspend Mode Entry
\
14. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2
T3 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T4 T5 T6 T7 T8 T9 T2
T0
T1
CLK
Semiconductor Group
RAx RAx CAx
tCK2
CKE
CS
RAS
CAS
39
WE
BA
AP
Addr tRC
(Minimum Interval)
DQM
tRP
tRC
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Precharge Command All Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank A
Read Command Bank A
\
15. Self Refresh (Entry and Exit)
T2 T10 T11 T T T T T T T T T T T T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK tCKSR tSREX
Semiconductor Group
CKE
CS
RAS
CAS
40
WE
A11(BS)
A10
A0 - A9 tRC
DQM
DQ
Hi-Z
All Banks must be idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
\
16.1 Random Column Read (Page within same Bank) (1 of 3)
Burst Length = 4, CAS Latency = 1
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RAz CAx CAy RAz CAz
tCK1
CKE
CS
RAS
CAS
41
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
WE
BA
AP
RAw
Addr
RAw
CAw
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Read Command Command Bank A Bank A Activate Command Bank A
\
16.2 Random Column Read (Page within same Bank) (2 of 3)
Burst Length = 4, CAS Latency = 2
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RAz CAw CAx CAy RAz CAz
tCK2
CKE
CS
RAS
CAS
42
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A
WE
BA
AP
RAw
Addr
RAw
DQM
DQ
Hi-Z
Az0
Az1
Az2
Az3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Activate Command Bank A
Read Command Bank A
\
16.3 Random Column Read (Page within same Bank) (3 of 3)
Burst Length = 4, CAS Latency = 3
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RAz CAw CAx CAy RAz CAz
tCK3
CKE
CS
RAS
CAS
43
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
WE
BA
AP
RAw
Addr
RAw
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
\
17.1 Random Column Write (Page within same Bank) (1 of 3)
Burst Length = 4, CAS Latency = 1
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RBz CBx CBy RBz CBz
tCK1
CKE
CS
RAS
CAS
44
Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B
WE
BA
AP
RBw
Addr
RBw
CBw
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B Write Command Bank B
Write Command Bank B
18.1 Random Row Read (Interleaving Banks) (1 of 3)
Burst Length = 8, CAS Latency = 1
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
Semiconductor Group
RAx RBy RAx CAx RBy CBy
CLK
tCK1
CKE
High
CS
RAS
CAS
45
WE
A11(BS)
A10
RBx
A0 - A9 tRP
RBx
CBx
tRCD tAC1
DQM
DQ
Bx1 Bx2 Bx3 Bx4 Bx5
Hi-Z Bx6
Bx0
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
By2
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B Read Command Bank B
Activate Precharge Command Command Bank A Bank B Activate Read Command Command BankB Bank A
Read Command Bank B
Precharge Command Bank A
18.2 Random Row Read (Interleaving Banks) (2 of 3)
Burst Length = 8, CAS Latency = 2
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RAx RBy RAx CAx RBy CBy
tCK2
CKE
High
CS
RAS
CAS
46
WE
A11(BS)
A10
RBx
A0 - A9 tAC2
RBx
CBx
DQM
tRCD
tRP
DQ
Bx0 Bx1 Bx2 Bx3
Hi-Z
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Command Bank B Read Command Bank A
Activate Command Bank B
Read Command Bank B
18. 3 Random Row Read (Interleaving Banks) (3 of 3)
Burst Length = 8, CAS Latency = 3
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
Semiconductor Group
RAx RBy CBx RAx CAx RBy CBy
CLK
tCK3
CKE
High
CS
RAS
CAS
47
WE
A11(BS)
A10
RBx
A0 - A9 tAC3
RBx
DQM
tRCD
tRP
DQ
Bx0 Bx1
Hi-Z
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
19.1 Random Row Write (Interleaving Banks) (1 of 3)
Burst Length = 8, CAS Latency = 1
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RBx RAy RBx CBx RAy CAy
tCK1
CKE
High
CS
RAS
CAS
48
WE
A11(BS)
A10
RAx
A0 - A9
RAx
CAx
tRCD
tRP
tDPL
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
DAy0 DAy1 DAy2 DAy3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Activate Command Bank B Write Command Bank B
Write Command Bank A
Precharge Command Bank A Activate Command Bank A
Precharge Command Bank B
Write Command Bank A
19.2 Random Row Write (Interleaving Banks) (2 of 3)
Burst Length = 8, CAS Latency = 2
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
Semiconductor Group
RBx RAy RBx CBx RAy CAy
CLK
tCK2
CKE
High
CS
RAS
CAS
49
WE
A11(BS)
A10
RAx
A0 - A9 tDPL
RAx
CAX CAy
tRCD
DQM
tRP
tDPL
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Write Command Bank A Precharge Command Bank B
19.3 Random Row Write (Interleaving Banks) (3 of 3)
Burst Length = 8, CAS Latency = 3
T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RBx RAy CAX RBx CBx RAy CAy
tCK3
CKE
High
CS
RAS
CAS
50
WE
A11(BS)
A10
RAx
A0 - A9
RAx
tRCD
tDPL
tRP
tDPL
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
\
17.2 Random Column Write (Page within same Bank) (2 of 3)
Burst Length = 4, CAS Latency = 2
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RBz RAw CBz CBx CBy RBz RAw CBz CAx
tCK2
CKE
CS
RAS
CAS
51
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
WE
BA
AP
RBz
Addr
RBz
DQM
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
\
17.3 Random Column Write (Page within same Bank) (3 of 3)
Burst Length = 4, CAS Latency = 3
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T2 T10 T11 T3 T4 T5 T6 T7 T8 T9
T0
T1
CLK
Semiconductor Group
RBz CBz CBx CBy RBz CBz
tCK3
CKE
CS
RAS
CAS
52
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Command Bank B Write Command Bank B Write Command Bank B
WE
BA
AP
RBz
Addr
RBz
DQM
DQ
Hi-Z
DBz0 DBz1
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
\
20.1 Full Page Read Cycle (1 of 3)
Burst Length = Full Page, CAS Latency = 1
T T T T T T T T T T T T T T T T T T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBy CBx RBy
tCK1
CKE
High
CS
RAS
CAS
53
WE
BA
AP
RAx
RBx
Addr
RAx
CAx
RBx
DQM
tRRD
tRP
DQ
Ax+1 Ax+2 Ax-2 Ax-1 Ax
Hi-Z
Ax
Ax+1
Bx
Bx+1 Bx+2
Bx+3
Bx+4 Bx+5
Bx+6
Bx+7
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Activate Command Command Bank B Bank A Read Command Bank A
The burst counter wraps from the highest order page address back to zero during this time interval.
Read Command Bank B
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Burst Stop bursting beginning with the starting address. Command
Precharge Command Bank B Activate Command Bank B
\
20.2 Full Page Read Cycle (2 of 3)
Burst Length = Full Page, CAS Latency = 2
T5 T T T T T T T T T T T T T T6 T T T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBx RBy RBx CBx RBy
tCK2
CKE
High
CS
RAS
CAS
54
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
WE
BA
AP
RAx
Addr
RAx
CAx
DQM
tRP
DQ
Hi-Z
Bx+3 Bx+4
Bx+5
Bx+6
Activate Command Bank A
Read Command Bank A
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Precharge Command Bank B Burst Stop Command
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank B
\
20.3 Full Page Read Cycle (3 of 3)
Burst Length = Full Page, CAS Latency = 3
T5 T T T T T T T T T T T T T T6 T7 T8 T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBx RBy CAx RBx CBx RBy
tCK3
CKE
High
CS
RAS
CAS
55
WE
BA
AP
RAx
Addr
RAx
DQM
tRRD
DQ
Ax Ax+1
Hi-Z
Ax+2 Ax-2
Ax-1 Read Command Bank B
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3 Bx+4
Bx+5
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A Activate Command Bank B
Read Command Bank A
Full Page burst operation does not terminate when the length is Precharge satisfied; the burst counter Command increments and continues Bank B The burst counter wraps bursting beginning with from the highest order the starting address. page address back to zero Burst Stop during this time interval. Command
Activate Command Bank B
\
21.1 Full Page Write Cycle (1 of 3)
Burst Length = Full Page, CAS Latency = 1
T T T T T T T T T T T T T T T T T T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBy CBx RBy
tCK1
CKE
High
CS
RAS
CAS
56
The burst counter wraps from the highest order page address back to zero during this time interval. Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
WE
BA
AP
RAx
RBx
Addr
RAx
CAx
RBx
DQM
DQ
Hi-Z
DAx DAx+1 DAx+2 DAx+2 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7
Data is ignored.
Precharge Command Bank B Burst Stop Command Activate Command Bank B
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Page Length: 2Mb x 4I/O x 2 Banks = 1024 1Mb x 8I/O x 2 Banks = 512 512kb x 16I/O x 2 Banks = 256
Activate Command Activate Bank B Command Bank A Write Command Bank A
\
21.2 Full Page Write Cycle (2 of 3)
Burst Length = Full Page, CAS Latency = 2
T5 T T T T T T T T T T T T T T T T T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBx RBy RBx CBx RBy
tCK2
CKE
High
CS
RAS
CAS
57
WE
BA
AP
RAx
Addr
RAx
CAx
DQM
DQ
Hi-Z
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Write Command Bank A
Activate Write Command Precharge Command Data is ignored. Command Bank B Bank B Bank B The burst counter wraps Full Page burst operation does not from the highest order terminate when the burst length is satisfied; page address back to zero Burst Stop the burst counter increments and continues during this time interval. bursting beginning with the starting address. Command
Activate Command Bank B
\
21.3 Full Page Write Cycle (3 of 3)
Burst Length = Full Page, CAS Latency = 3
T5 T T T T T T T T T T T T T T6 T T T T2 T3 T4
T0
T1
CLK
Semiconductor Group
RBx RBy CAx RBx CBx RBy
tCK3
CKE
High
CS
RAS
CAS
58
Write Command Bank A
WE
BA
AP
RAx
Addr
RAx
DQM
Data is ignored. DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
DQ
Hi-Z
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A
Activate Write Command Precharge Command Full Page burst operation does not Command Bank B Bank B terminate when the length is Bank B satisfied; the burst counter The burst counter wraps increments and continues from the highest order bursting beginning with page address back to zero Burst Stop the starting address. during this time interval. Command
Activate Command Bank B
\
22.1 Precharge Termination of a Burst (1 of 3)
T2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T3 T4 T5 T6 T7 T8 T9
Burst Length = Full Page, CAS Latency = 1
T0
T1
CLK
Semiconductor Group
RAy RAz CAx RAy CAy RAz CAz
tCK1
CKE
CS
RAS
CAS
59
WE
BA
AP
RAx
Addr tRP
RAx
tRP
DQM
Precharge Termination of a Read Burst.
DQ
DAx0 DAx1 DAx2 DAx3 DAx4
Hi-Z
Ay0
Ay1
Ay2
DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Activate Command Bank A Write Command Bank A
Read Precharge Command Command Bank A Bank A Precharge Termination Activate of a Write Burst. Command Write data is masked. Bank A
Precharge Command Bank A
Write Command Bank A Activate Command Bank A
\
22.2 Precharge Termination of a Burst (2 of 3)
T2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T3 T4 T5 T6 T7 T8 T9
Burst Length = 8 or Full Page, CAS Latency = 2
T0
T1
CLK
Semiconductor Group
RAy RAz RAy CAy RAz CAz
tCK2
CKE
High
CS
RAS
CAS
60
WE
BA
AP
RAx
Addr tRP
RAx
CAx
tRP
tRP
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate Command Bank A
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked.
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A Precharge Termination of a Read Burst.
\
22.3 Precharge Termination of a Burst (3 of 3)
T2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T3 T4 T5 T6 T7 T8 T9
Burst Length = 4,8 or Full Page, CAS Latency = 3
T0
T1
CLK
Semiconductor Group
RAy RAz CAx RAy CAy RAz
tCK3
CKE
High
CS
RAS
CAS
61
WE
BA
AP
RAx
Addr tRP
RAx
tRP
DQM
DQ
DAx0
Hi-Z
Ay0
Ay1
Ay2
Activate Command Bank A Write Command Bank A Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A Precharge Termination of a Read Burst.
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Write Data is masked
Precharge Termination of a Write Burst.
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
Complete List of Operation Commands SDRAM FUNCTION TRUTH TABLE
CURRENT STATE 1 Idle
CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L
RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L L
CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H H L
WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L H L X
BS X X BS BS BS BS X OpX X BS BS BS BS X X X BS BS BS BS BS X X X BS BS BS BS BS X X X BS BS X BS BS X
Addr X X X X RA AP X Code X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X X X X AP X
ACTION NOP or Power Down NOP ILLEGAL2 ILLEGAL2 Row (&Bank) Active; Latch Row Address NOP4 5 Auto-Refresh or Self-Refresh 5 Mode reg. Access NOP NOP Begin Read; Latch CA; Determine AP Begin Write; Latch CA; Determine AP ILLEGAL2 Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, New Read, Determine 3 AP Term Burst, Start Write, Determine 3 AP ILLEGAL2 Term Burst, Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, Start Read, Determine 3 AP Term Burst, New Write, Determine 3 AP ILLEGAL2 Term Burst, Precharge3 ILLEGAL NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL
Row Active
Read
Write
Read with Auto Precharge
Semiconductor Group
62
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT STATE 1 Write with Auto Precharge CS H L L L L L L L RAS X H H H H L L L X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L CAS X H H L L H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X WE X H L H L H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BS X X BS BS X BS BS X X X BS BS BS BS X X X BS BS BS BS X X X BS BS BS BS X X X X X X X X X X X Addr X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X X X X X X ACTION NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRP NOP;> Idle after tRP ILLEGAL2 ILLEGAL2 ILLEGAL2 NOP4 ILLEGAL NOP;> Row Active after tRCD NOP;> Row Active after tRCD ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP NOP ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRC NOP;> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL
Precharging H L L L L L L Row Activating H L L L L L L H L L L L L L H L L L L H L L L L
Write Recovering
Refreshing
Mode Register Accessing
Semiconductor Group
63
HYB39S16400/800/160BT-8/-10 16MBit Synchronous DRAM
CLOCK ENABLE (CKE) TRUTH TABLE:
STATE(n) SelfRefresh6
CKE n-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L
CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L
CS X H L L L L X X H L L L L X X H L L L L L L X X X X X
RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X
CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X
WE X X H L X X X X X H L X X X X X H L X X H L X X X X X
Addr X X X X X X X X X X X X X X X X X X X X X X X X X X X
ACTION INVALID EXIT Self-Refresh, Idle after tRC EXIT Self-Refresh, Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID EXIT Power-Down, > Idle. EXIT Power-Down, > Idle. ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low-Power Mode) Refer to the function truth table Enter Power- Down Enter Power- Down ILLEGAL ILLEGAL ILLEGAL Enter Self-Refresh ILLEGAL NOP Refer to the function truth table 8 Begin Clock Suspend next cycle 8 Exit Clock Suspend next cycle . Maintain Clock Suspend.
Power-Down
All. Banks Idle7
Any State other than listed above
ABBREVIATIONS: RA = Row Address CA = Column Address BS = Bank Address AP = Auto Precharge
Notes for SDRAM function truth table : 1. Current State is state of the bank determined by BS. All entries assume that CKE was active cycle. (HIGH) during the preced clock ing
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP). 5. Illegal if any bank is not Idle. 6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 8. Must be legal command as defined in the SDRAM function truth table.
Semiconductor Group
64

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